MC68HC705J1ACPE Datasheet, PDF (88/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
Addr. Register Name
Bit 7
6
5
Read:
Port A Data Register
PA7
PA6
PA5
$0000
(PORTA) Write:
See page 89.
Reset:
$0001
Read: 0
Port B Data Register
(PORTB) Write:
See page 92.
Reset:
0
PB5
$0004
Read:
Data Direction Register A
(DDRA) Write:
See page 90.
Reset:
DDRA7
0
DDRA6
0
DDRA5
0
Read: 0
Data Direction Register B
$0005
(DDRB) Write:
See page 93.
Reset: 0
0
DDRB5
0
0
$0010
Read:
Pulldown Register A
(PDRA) Write:
See page 91.
Reset:
PDIA7
0
PDIA6
0
PDIA5
0
$0011
Read:
Pulldown Register B
(PDRB) Write:
See page 94.
Reset:
PDIB5
0
= Unimplemented
4
3
PA4
PA3
Unaffected by reset
PB4
PB3
Unaffected by reset
DDRA4 DDRA3
0
0
DDRB4 DDRB3
0
0
PDIA4
0
PDIA3
0
PDIB4
0
PDIB3
0
2
PA2
PB2
DDRA2
0
DDRB2
0
PDIA2
0
PDIB2
0
1
PA1
PB1
DDRA1
0
DDRB1
0
PDIA1
0
PDIB1
0
Bit 0
PA0
PB0
DDRA0
0
DDRB0
0
PDIA0
0
PDIB0
0
Figure 6-1. Parallel I/O Port Register Summary
Technical Data
MC68HC705J1A — Rev. 4.0
Parallel Input/Output (I/O) Ports
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