MC68HC705J1ACPE Datasheet, PDF (91/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
Port A
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 6-1 summarizes the operation
of the port A pins.
Table 6-1. Port A Pin Operation
Data Direction Bit
I/O Pin Mode
0
Input, high-impedance
1
Output
1. Writing affects the data register but does not affect input.
Accesses to Data Bit
Read
Pin
Write
Latch⁽¹⁾
Latch
Latch
6.3.3 Pulldown Register A
Pulldown register A (PDRA) inhibits the pulldown devices on port A pins
programmed as inputs.
NOTE: If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port A pins as inputs with disabled pulldown devices.
Address: $0010
Bit 7
6
5
4
3
2
1
Read:
Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 6-5. Pulldown Register A (PDRA)
Bit 0
PDIA0
0
PDIA[7:0] — Pulldown Inhibit A Bits
PDIA[7:0] disable the port A pulldown devices. Reset clears
PDIA[7:0].
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
MC68HC705J1A — Rev. 4.0
Parallel Input/Output (I/O) Ports
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Technical Data