MC68HC705J1ACPE Datasheet, PDF (104/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
8.3.1 IRQ/V_PP Pin
An interrupt signal on the IRQ/V_PP pin latches an external interrupt
request. The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If edge- and level-sensitive triggering is selected, a falling edge or a low
level on the IRQ/V_PP pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. An external interrupt request is latched as long as any
source is holding the IRQ/V_PP pin low.
If level-sensitive triggering is selected, the IRQ/V_PP input requires an
external resistor to V_DD for wired-OR operation. If the IRQ/V_PP pin is not
used, it must be tied to the V_DD supply.
If edge-sensitive-only triggering is selected, a falling edge on the
IRQ/V_PP pin latches an external interrupt request. A subsequent external
interrupt request can be latched only after the voltage level on the
IRQ/V_PP pin returns to logic 1 and then falls again to logic 0.
The IRQ/V_PP pin contains an internal Schmitt trigger as part of its input
to improve noise immunity. The voltage on this pin can affect the mode
of operation and should not exceed V_DD.
8.3.2 Optional External Interrupts
The inputs for the lower four bits of port A (PA0–PA3) can be connected
to the IRQ pin input of the CPU if enabled by the PIRQ bit in the mask
option register. This capability allows keyboard scan applications where
the transitions or levels on the I/O pins will behave the same as the
IRQ/V_PP pin except for the inverted phase (logic 1, rising edge). The
active state of the IRQ/V_PP pin is a logic 0 (falling edge).
The PA0–PA3 pins are selected as a group to function as IRQ interrupts
and are enabled by the IRQE bit in the IRQ status and control register.
The PA0–PA3 pins can be positive-edge triggered only or positive-edge
and high-level triggered.
Technical Data
MC68HC705J1A — Rev. 4.0
External Interrupt Module (IRQ)
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