MC68HC705J1ACPE Datasheet, PDF (93/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
Port B
6.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is
an input or an output.
Address: $0005
Bit 7
6
5
4
3
2
1
Read: 0
Write:
0
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 6-7. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB[5:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[5:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 6-8 shows the I/O logic of port B.
READ DDRB
WRITE DDRB
WRITE PORTB
DDRBx
PBx
READ PORTB
WRITE PDRB
PDRBx
RESET
SWPDI
Figure 6-8. Port B I/O Circuitry
PBx
100-µA
PULLDOWN
MC68HC705J1A — Rev. 4.0
Parallel Input/Output (I/O) Ports
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Technical Data