MC68HC705J1ACPE Datasheet, PDF (82/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Low-Power Modes
Freescale Semiconductor, Inc.
5.4.2 CPU
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the
oscillator stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts
• Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
5.4.3 COP Watchdog
The STOP instruction:
• Clears the COP watchdog counter
• Disables the COP watchdog clock
NOTE:
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
After exit from stop mode by external interrupt, the COP watchdog
counter immediately begins counting from $0000 and continues
counting throughout the oscillator stabilization delay.
NOTE: Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
Technical Data
MC68HC705J1A — Rev. 4.0
Low-Power Modes
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