MC68HC705J1ACPE Datasheet, PDF (90/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
6.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output.
Address: $0004
Bit 7
6
5
4
3
2
1
Read:
DDRA7
Write:
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
Reset: 0
0
0
0
0
0
0
Figure 6-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 6-4 shows the I/O logic of port A.
READ DDRA
WRITE DDRA
WRITE PORTA
READ PORTA
DDRAx
PAx
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
PAx
(PA0–PA3 TO
IRQ MODULE)
WRITE PDRA
PDRAx
RESET
SWPDI
Figure 6-4. Port A I/O Circuitry
100-µA
PULLDOWN
Technical Data
MC68HC705J1A — Rev. 4.0
Parallel Input/Output (I/O) Ports
For More Information On This Product,
Go to: www.freescale.com