MC68HC705J1ACPE Datasheet, PDF (72/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Resets and Interrupts
4.3.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 t_cyc generates an external
reset. A Schmitt trigger senses the logic level at the RESET pin.
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
$07FE $07FE $07FE $07FE $07FF NEW PC NEW PC
INTERNAL
DATA BUS
NEW
PCH
NEW
PCL
DUMMY
OP
CODE
t_RL
RESET
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 4-3. External Reset Timing
Table 4-1. External Reset Timing
Characteristic
RESET pulse width
Symbol Min
t_RL
1.5
Max
—
Unit
t_cyc
4.3.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the
COP register at location $07F0.
4.3.4 Illegal Address Reset
An opcode fetch from an address not in random-access memory (RAM)
or erasable, programmable read-only memory (EPROM) generates a
reset.
Technical Data
MC68HC705J1A — Rev. 4.0
Resets and Interrupts
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