MC68HC705J1ACPE Datasheet, PDF (94/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 6-2 summarizes the operation
of the port B pins.
Table 6-2. Port B Pin Operation
Data Direction Bit
0
1
I/O Pin Mode
Input, high-impedance
Output
Accesses to Data Bit
Read
Pin
Write
Latch⁽¹⁾
Latch
Latch
1. Writing affects the data register, but does not affect input.
6.4.3 Pulldown Register B
Pulldown register B (PDRB) inhibits the pulldown devices on port B pins
programmed as inputs.
NOTE: If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port B pins as inputs with disabled pulldown devices.
Address: $0011
Bit 7
6
5
4
3
2
1
Read:
Write:
PDIB5 PDIB4 PDIB3 PDIB2 PDIB1
Reset:
0
0
0
0
0
= Unimplemented
Figure 6-9. Pulldown Register B (PDRB)
Bit 0
PDIB0
0
PDIB[7:0] — Pulldown Inhibit B Bits
PDIB[7:0] disable the port B pulldown devices. Reset clears
PDIB[7:0].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Technical Data
MC68HC705J1A — Rev. 4.0
Parallel Input/Output (I/O) Ports
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