MC68HC705J1ACPE Datasheet, PDF (74/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Resets and Interrupts
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/V_PP pin can latch another interrupt
request during the interrupt service routine. As soon as the I bit is cleared
during the return from interrupt, the CPU can recognize the new interrupt
request. Figure 4-4 shows the IRQ/V_PP pin interrupt logic.
IRQ
PA3
PA2
PA1
PA0
PIRQ
(MOR)
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
V_DD
D ^IRQ Q
LATCH
CK
CLR
IRQF
IRQE
RESET
IRQ VECTOR FETCH
IRQR
Figure 4-4. External Interrupt Logic
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register
enables pins PA0–PA3 to function as external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register
controls interrupt triggering sensitivity of external interrupt pins. The
IRQ/V_PP pin can be negative-edge triggered only or negative-edge and
low-level triggered. Port A external interrupt pins can be positive-edge
triggered only or both positive-edge and high-level triggered. The
level-sensitive triggering option allows multiple external interrupt
sources to be wire-ORed to an external interrupt pin. An external
interrupt request, shown in Figure 4-5, is latched as long as any source
is holding an external interrupt pin low.
Technical Data
MC68HC705J1A — Rev. 4.0
Resets and Interrupts
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