MC68HC705J1ACPE Datasheet, PDF (41/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Memory
Mask Option Register
Take these steps to program the mask option register:
1. Apply the programming voltage, V_PP, to the IRQ/V_PP pin.
2. Write to the MOR.
3. Set the MPGM bit and wait for a time, t_MPGM.
4. Clear the MPGM bit.
5. Reset the MCU.
Address: $07F1
Bit 7
6
5
4
3
2
1
Read:
SOSCD EPMSEC OSCRES SWAIT
Write:
SWPDI
PIRQ
LEVEL
Reset:
Unaffected by reset
Figure 2-4. Mask Option Register (MOR)
Bit 0
COPEN
SOSCD — Short Oscillator Delay Bit
The SOSCD bit controls the oscillator stabilization counter. The
normal stabilization delay following reset or exit from stop mode is
4064 t_cyc. Setting SOSCD enables a short oscillator stabilization
delay.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
EPMSEC — EPROM Security Bit
The EPMSEC bit controls access to the EPROM/OTPROM.
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
OSCRES — Oscillator Internal Resistor Bit
The OSCRES bit enables a 2-MΩ internal resistor in the oscillator
circuit.
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
NOTE: Program the OSCRES bit to logic 0 in devices using RC oscillators.
MC68HC705J1A — Rev. 4.0
Memory
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Technical Data