MC68HC705J1ACPE Datasheet, PDF (37/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Memory
RAM
Addr.
$0019
↓
$001E
Register Name
Unimplemented
Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
$001F
Reserved
R
R
R
R
R
R
R
R
$07F0
$07F1
Read:
COP Register
(COPR) Write:
See page 99.
Reset:
Read:
Mask Option Register
(MOR) Write:
See page 41.
Reset:
SOSCD
EPMSEC OSCRES
SWAIT SWPDI
Unaffected by reset
= Unimplemented R = Reserved
PIRQ
Figure 2-2. I/O Register Summary (Sheet 3 of 3)
COPC
0
LEVEL COPEN
2.5 RAM
The 64 addresses from $00C0 to $00FF serve as both the user RAM and
the stack RAM. Before processing an interrupt, the central processor
unit (CPU) uses five bytes of the stack to save the contents of the CPU
registers. During a subroutine call, the CPU uses two bytes of the stack
to store the return address. The stack pointer decrements when the CPU
stores a byte on the stack and increments when the CPU retrieves a byte
from the stack.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
MC68HC705J1A — Rev. 4.0
Memory
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Technical Data