MC68HC705J1ACPE Datasheet, PDF (71/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
4.3.1 Power-On Reset
NOTE:
A positive transition on the V_DD pin generates a power-on reset.
The power-on reset is strictly for power-up conditions and cannot be
used to detect drops in power supply voltage.
A 4064-t_cyc (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If any reset source is active
at the end of this delay, the MCU remains in the reset condition until all
reset sources are inactive.
V_DD
(NOTE 1)
OSC1 PIN
OSCILLATOR STABILIZATION DELAY
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
$07FE $07FE $07FE $07FE $07FE $07FE $07FF
INTERNAL
DATA BUS
NEW PCH NEW PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 4-2. Power-On Reset Timing
MC68HC705J1A — Rev. 4.0
Resets and Interrupts
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Technical Data