MC68HC705J1ACPE Datasheet, PDF (114/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Multifunction Timer Module
interrupt request to be generated. To prevent this occurrence, clear the
COP timer before changing RT1 and RT0.
Table 9-1. Real-Time Interrupt Rate Selection
RT1:RT0
Number
of Cycles
to RTI
RTI
Period⁽¹⁾
00
2¹⁴ = 16,384
8.2 ms
01
2¹⁵ = 32,768
16.4 ms
10
2¹⁶ = 65,536
32.8 ms
11
2¹⁷ = 131,072 ^{65.5 ms}
1. At 2-MHz bus, 4-MHz XTAL, 0.5 µs per cycle
Number
of Cycles
to COP Reset
2¹⁷ = 131,072
2¹⁸ = 262,144
2¹⁹ = 524,288
2²⁰ = 1,048,576
COP Timeout
Period⁽¹⁾
65.5 ms
131.1 ms
262.1 ms
524.3 ms
9.5.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register (TCR) shown in Figure 9-4.
Address: $0009
Bit 7
6
5
4
3
2
1
Read: TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 9-4. Timer Counter Register (TCR)
Bit 0
TMR0
0
Power-on clears the entire counter chain and the internal clock begins
clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in
the mask option register is set), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Technical Data
MC68HC705J1A — Rev. 4.0
Multifunction Timer Module
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