MC68HC05P9A Datasheet, PDF (96/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Timer
Timer Status
Register
Freescale Semiconductor, Inc.
IEDG — Input Edge
The state of this read/write bit determines whether a positive or
negative transition on the PD7/TCAP pin triggers a transfer of the
contents of the timer registers to the input capture registers. Reset
has no effect on the IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
OLVL — Output Level
The state of this read/write bit determines whether a logic 1 or a logic
0 appears on the TCMP pin when a successful output compare
occurs. Reset clears the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
The timer status register (TSR) contains flags for the following events:
• An active signal on the PD7/TCAP pin, transferring the contents of
the timer registers to the input capture registers
• A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
• A timer rollover from $FFFF to $0000
$0013 Bit 7
6
5
4
3
2
1
Bit 0
Read: ICF
OCF
TOF
0
0
0
0
0
Write:
Reset: U
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 52. Timer Status Register (TSR)
16-tim1ic1oc_a
96
Timer
MOTOROLA
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