MC68HC05P9A Datasheet, PDF (113/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
SIOP
I/O Registers
Clearing SPE during a transmission aborts the transmission, resets
the bit counter, and returns the port to its normal I/O function. Reset
clears SPE.
1 = SIOP enabled
0 = SIOP disabled
MSTR — Master Mode Select
This read/write bit configures the SIOP for master mode. Setting
MSTR initializes the PB7/SCK pin as the serial clock output. Clearing
MSTR initializes the PB7/SCK pin as the serial clock input. MSTR can
be set at any time regardless of the state of SPE. Reset clears MSTR.
1 = Master mode selected
0 = Slave mode selected
15-mc68hc05p9a
MOTOROLA
SIOP
113
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