MC68HC05P9A Datasheet, PDF (78/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports
Freescale Semiconductor, Inc.
When bit DDRDx is a logic 1, reading address $0003 reads the PDx data
latch. When bit DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 16 summarizes the operation
of the port D pins.
Table 18. Port D Pin Operation
Data Direction Bit
0
I/O Pin Mode
Input, Hi-Z⁽¹⁾
Accesses to Data Bit
Read
Pin
Write
Latch⁽²⁾
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
18-mc68hc05p9a
78
Parallel I/O Ports
MOTOROLA
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