MC68HC05P9A Datasheet, PDF (108/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

SIOP
PB5/SDO
PB6/SDI
Freescale Semiconductor, Inc.
Figure 61 shows the timing relationships among the serial clock, data
input, and data output. The state of the serial clock between
transmissions is a logic 1. The first falling edge on the PB7/SCK pin
signals the beginning of a transmission, and data appears at the
PB5/SDO pin. Data is captured at the PB6/SDI pin on the rising edge of
the serial clock, and the transmission ends on the eighth rising edge of
the serial clock.
SERIAL CLOCK
SAMPLE INPUT
DATA OUTPUT
(MSB-FIRST OPTION)
DATA OUTPUT
(LSB-FIRST OPTION)
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB
Figure 61. SIOP Data/Clock Timing
The PB5/SDO pin is the SIOP data output. Between transfers, the state
of the PB5/SDO pin reflects the value of the last bit shifted out on the
previous transmission, if there was one. To preset the beginning state,
write to the corresponding port data bit before enabling the SIOP. On the
first falling edge on the PB7/SCK pin, the first data bit to be shifted out
appears at the PB5/SDO pin.
The PB6/SDI pin is the SIOP data input. Valid SDI data must be present
for an SDI setup time, t_S, before the rising edge of the serial clock and
must remain valid for an SDI hold time, t_H, after the rising edge of the
serial clock. (See Table 22 and Table 23.)
10-mc68hc05p9a
108
SIOP
MOTOROLA
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