MC68HC05P9A Datasheet, PDF (51/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

External Reset
Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
V_DD
(NOTE 1)
OSC1 PIN
4064 t_CYC
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE 1FFE 1FFE 1FFE 1FFE 1FFE 1FFF
INTERNAL
DATA BUS
NEW NEW
PCH
PCL
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 18. Power-On Reset Timing
A logic 0 applied to the RESET pin for one and one-half t_CYC generates
an external reset. A Schmitt trigger senses the logic level at the RESET
pin.
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE 1FFE 1FFE 1FFE 1FFF NEW PC NEW PC
INTERNAL
DATA BUS
NEW
PCH
NEW
PCL
DUMMY
OP
CODE
t_RL
RESET
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 19. External Reset Timing
Table 11. External Reset Timing
Characteristic
RESET Pulse Width
Symbol Min
t_RL
1.5
Max
—
Unit
t_CYC
7-mc68hc05p9a
MOTOROLA
Resets and Interrupts
51
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