MC68HC05P9A Datasheet, PDF (70/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports
Freescale Semiconductor, Inc.
Port A I/O Pin
Interrupts/Pullups
If the port A interrupt/pullup enabled mask option is selected the
PA0–PA7 pins will function as external interrupt pins when configured as
inputs. (See External Interrupt on page 53.)
Port B
Port B is a 3-bit I/O port that shares its pins with the serial I/O port
(SIOP).
NOTE: Do not use port B for general-purpose I/O while the SIOP is enabled.
Port B Data
Register (PORTB)
The port B data register contains a latch for each of the three port B pins.
$0001 Bit 7
6
5
4
3
2
Read:
0
0
0
PB7
PB6
PB5
Write:
Reset:
Unaffected by reset
Alternate
Function:
SCK
SDI
SDO
1
Bit 0
0
0
= Unimplemented
Figure 32. Port B Data Register (PORTB)
PB[7:5] — Port B Data Bits
These read/write bits are software programmable bits. Data direction
of each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
NOTE:
Writing to data direction register B does not affect the data direction of
port B pins that are being used by the SIOP. However, data direction
register B always determines whether reading port B returns the states
of the latches or the states of the pins.
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Parallel I/O Ports
MOTOROLA
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