MC68HC05P9A Datasheet, PDF (75/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel I/O Ports
Port C
READ DATA DIRECTION REGISTER C ($0006)
WRITE DATA DIRECTION REGISTER C ($0006)
RESET
WRITE PORT C DATA REGISTER ($0002)
DDRCx
PCx
READ PORT C DATA REGISTER ($0002)
HIGH CURRENT SOURCE/SINK
CAPABILITY (PINS PA0–PA1 ONLY)
PCx
PC0–PC1 High
Current
Sink/Source
Capability
Figure 37. Port C I/O Logic
Writing a logic 1 to a DDRC bit enables the output buffer for the
corresponding port C pin; a logic 0 disables the output buffer.
When bit DDRCx is a logic 1, reading address $0002 reads the PCx data
latch. When bit DDRCx is a logic 0, reading address $0002 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 16 summarizes the operation
of the port C pins.
Table 17. Port C Pin Operation
Data Direction Bit
0
I/O Pin Mode
Input, Hi-Z⁽¹⁾
Accesses to Data Bit
Read
Pin
Write
Latch⁽²⁾
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
The outputs for the lower two bits of port C (PC0–PC1) can source/sink
relatively high current. (See 5.0 V DC Electrical Characteristics on
page 130 and 3.3 V DC Electrical Characteristics on page 132 for
details.)
15-mc68hc05p9a
MOTOROLA
Parallel I/O Ports
75
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