MC68HC05P9A Datasheet, PDF (54/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets and Interrupts
MASK OPTION
EDGE AND LEVEL
EDGE ONLY
FROM OTHER
PORT B PINS
IRQ
V_DD
DQ
CQ
R
I BIT
(FROM CCR)
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 20. External Interrupt Logic
EXTERNAL
INTERRUPT
REQUEST
Setting the I bit in the condition code register disables external interrupts.
Interrupt triggering sensitivity of the IRQ pin is a mask option. The IRQ
pin can be negative-edge triggered or negative-edge- and low-level
triggered. The level-sensitive triggering option allows multiple external
interrupt sources to be wire-ORed to the IRQ pin. An external interrupt
request, shown in Figure 21, is latched as long as any source is holding
the IRQ pin low.
IRQ/V_PP PIN
t_ILIL
t_ILIH
IR.Q₁
t_ILIH
.
.
IRQ_n
IRQ (INTERNAL)
Figure 21. External Interrupt Timing
10-mc68hc05p9a
54
Resets and Interrupts
MOTOROLA
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