MC68HC05P9A Datasheet, PDF (45/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
CPU
Instruction Set
Source
Form
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Table 9. Instruction Set Summary (Continued)
Operation
Description
Effect on
CCR
H I NZC
Unconditional Jump
Jump to Subroutine
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
Logical Shift Right
Unsigned Multiply
Negate Byte (Two’s Complement)
No Operation
Logical OR Accumulator with Memory
DIR BC dd 2
EXT CC hh ll 3
PC ← Jump Address
— — — — — IX2 DC ee ff 4
IX1 EC ff 3
IX FC
2
DIR BD dd 5
PC ← (PC) + n (n = 1, 2, or 3)
EXT CD hh ll 6
Push (PCL); SP ← (SP) – 1
— — — — — IX2 DD ee ff 7
Push (PCH); SP ← (SP) – 1
IX1 ED ff 6
PC ← Effective Address
IX FD
5
IMM A6 ii 2
DIR B6 dd 3
A ← (M)
— — ¤ ¤ — ^{EXT C6 hh ll 4}
IX2 D6 ee ff 5
IX1 E6 ff 4
IX F6
3
IMM AE ii 2
DIR BE dd 3
X ← (M)
— — ¤ ¤ — ^{EXT CE hh ll 4}
IX2 DE ee ff 5
IX1 EE ff 4
IX FE
3
DIR 38 dd 5
C
b7
0
b0
INH 48
3
— — ¤ ¤ ¤ INH 58
3
IX1 68 ff 6
IX 78
5
DIR 34 dd 5
0
b7
C
b0
INH 44
3
— — 0 ¤ ¤ INH 54
3
IX1 64 ff 6
IX 74
5
X : A ← (X) × (A)
0 — — — 0 INH 42
11
M ← –(M) = $00 – (M)
DIR 30 dd 5
A ← –(A) = $00 – (A)
INH 40
3
X ← –(X) = $00 – (X)
— — ¤ ¤ ¤ INH 50
3
M ← –(M) = $00 – (M)
IX1 60 ff 6
M ← –(M) = $00 – (M)
IX 70
5
— — — — — INH 9D
2
IMM AA ii 2
DIR BA dd 3
A ← (A) ∨ (M)
— — ¤ ¤ — ^{EXT CA hh ll 4}
IX2 DA ee ff 5
IX1 EA ff 4
IX FA
3
23-hc05cpu
MOTOROLA
CPU
45
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