MC68HC05P9A Datasheet, PDF (115/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
SIOP
I/O Registers
DCOL — Data Collision Flag
This clearable, read-only bit is automatically set if the SIOP data
register is accessed while a data transfer is in progress. Reading or
writing the SIOP data register while a transmission is in progress
causes invalid data to be transmitted or read. Clear DCOL by reading
the SIOP status register with SPIF set and then accessing the SIOP
data register. Because the clearing sequence accesses the SIOP
data register, the sequence has to be completed before another
transmission starts or DCOL is set again.
To clear DCOL when SPIF is not set, turn off the SIOP by writing a 0
to SPE and then turn it back on by writing a 1 to SPE. Reset clears
DCOL.
1 = Invalid access of SDR
0 = Valid access of SDR
SIOP Data Register
The SIOP data register (SDR) is both the transmit data register and the
receive data register. To read or write the SIOP data register, the SPE
bit in the SIOP control register must be set.
$000C Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Unaffected by reset
Figure 66. SIOP Data Register (SDR)
With the SIOP configured for master mode, writing to the SIOP data
register initiates a serial transfer. This register is not buffered. Writing to
the SIOP data register overwrites the previous contents. Reading or
writing to the SIOP data register while a transmission is in progress can
cause invalid data to be transmitted or received.
17-mc68hc05p9a
MOTOROLA
SIOP
115
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