MC68HC05P9A Datasheet, PDF (68/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports
Freescale Semiconductor, Inc.
Data Direction
Data direction register A determines whether each port A pin is an input
Register A (DDRA) or an output.
$0004 Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 30. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all eight port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 31 shows the I/O logic of port A.
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 16 summarizes the operation
of the port A pins.
Table 15. Port A Pin Operation
Data Direction Bit
0
I/O Pin Mode
Input, Hi-Z⁽¹⁾
Accesses to Data Bit
Read
Pin
Write
Latch⁽²⁾
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
8-mc68hc05p9a
68
Parallel I/O Ports
MOTOROLA
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