MC68HC05P9A Datasheet, PDF (61/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Low-Power Modes
Halt Mode
Halt Mode
NOTE:
Halt mode is NOT designed for intentional use. Halt mode is only
provided to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertently. This mode of operation is usually
achieved by invoking wait mode.
Execution of the STOP instruction when STOP is disabled mask option
is selected placing the MCU in this low-power mode. Halt mode
consumes the same amount of power as wait mode (both halt and wait
modes consume more power than stop mode).
In halt mode, the internal clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
the halt mode and resume normal operation. The halt mode also can be
exited when an IRQ external interrupt or external RESET occurs. When
exiting the halt mode, the internal clock will resume after a delay of one
to 4064 internal clock cycles. This varied delay time is the result of the
halt mode exit circuitry testing the oscillator stabilization delay timer (a
feature of the stop mode), which has been free-running (a feature of the
wait mode).
Figure 25 shows the sequence of events caused by the STOP/HALT
instruction.
7-mc68hc05p9a
MOTOROLA
Low-Power Modes
61
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