MC68HC05P9A Datasheet, PDF (71/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel I/O Ports
Port B
SCK — Serial Clock
When the SIOP is enabled, SCK is the SIOP clock output (in master
mode) or the SIOP clock input (in slave mode).
SDI — Serial Data Input
When the SIOP is enabled, SDI is the SIOP data input.
SDO — Serial Data Output
When the SIOP is enabled, SDO is the SIOP data output.
Data Direction
Register B (DDRB)
Data direction register B determines whether each port B pin is an input
or an output.
NOTE:
Enabling and then disabling the SIOP configures data direction register
B for SIOP operation and can also change the port B data register. After
disabling the SIOP, initialize data direction register B and the port B data
register as your application requires.
$0005 Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
DDRB7 DDRB6 DDRB5
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 33. Data Direction Register B (DDRB)
DDRB[7:5] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:5], configuring all three port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 34 shows the I/O logic of port B.
11-mc68hc05p9a
MOTOROLA
Parallel I/O Ports
71
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