MC68HC05P9A Datasheet, PDF (72/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports
Freescale Semiconductor, Inc.
READ DATA DIRECTION REGISTER B ($0005)
WRITE DATA DIRECTION REGISTER B ($0005)
RESET
DDRBx
WRITE PORT B DATA REGISTER ($0001)
PBx
PBx
READ PORT B DATA REGISTER ($0001)
Figure 34. Port B I/O Logic
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 16 summarizes the operation
of the port B pins.
Table 16. Port B Pin Operation
Data Direction Bit
0
I/O Pin Mode
Input, Hi-Z⁽¹⁾
Accesses to Data Bit
Read
Pin
Write
Latch⁽²⁾
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
12-mc68hc05p9a
72
Parallel I/O Ports
MOTOROLA
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