MC68HC05P9A Datasheet, PDF (55/158 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

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Resets and Interrupts
Interrupts
Table 12. External Interrupt Timing (V_DD = 5.0 Vdc)⁽¹⁾
Characteristic
Symbol Min Max Unit
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
t_ILIH
125
— ns
t_ILIL
Note⁽²⁾
—
t_CYC
1. V_DD = 5.0 Vdc ±10%, V_SS = 0 Vdc, T_A = T_L to T_H
2. The minimum t_ILIL should not be less than the number of interrupt service routine cycles
plus 19 t_CYC.
Table 13. External Interrupt Timing (V_DD = 3.3 Vdc)⁽¹⁾
Characteristic
Symbol Min Max Unit
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
t_ILIH
250
— ns
t_ILIL
Note⁽²⁾
—
t_CYC
1. V_DD = 3.3 Vdc ±10%, V_SS = 0 Vdc, T_A = T_L to T_H
2. The minimum t_ILIL should not be less than the number of interrupt service routine cycles
plus 19 t_CYC.
Timer Interrupts
The capture/compare timer can generate the following interrupts:
• Input capture interrupt
• Output compare interrupt
• Timer overflow interrupt
Setting the I bit in the condition code register disables timer interrupts.
Input Capture
Interrupt
An input capture interrupt request occurs if the input capture flag, ICF,
becomes set while the input capture interrupt enable bit, ICIE, is also set.
ICF is in the timer status register, and ICIE is in the timer control register.
Output Compare
Interrupt
An output compare interrupt request occurs if the output compare flag,
OCF, becomes set while the output compare interrupt enable bit, OCIE,
is also set. OCF is in the timer status register, and OCIE is in the timer
control register.
11-mc68hc05p9a
MOTOROLA
Resets and Interrupts
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