MC9S08EL32 Datasheet, PDF (88/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output Control
6.5.2.3 Port B Pull Enable Register (PTBPE)
R
W
Reset:
7
PTBPE7
0
6
PTBPE6
5
PTBPE5
4
PTBPE4
3
PTBPE3
2
PTBPE2
1
PTBPE1
0
0
0
0
0
0
Figure 6-13. Internal Pull Enable for Port B Register (PTBPE)
Table 6-11. PTBPE Register Field Descriptions
0
PTBPE0
0
Field
Description
7:0
PTBPE[7:0]
Internal Pull Enable for Port B Bits — Each of these control bits determines if the internal pull-up or internal
(pin interrupt only) pull-down device is enabled for the associated PTB pin. For port B pins that are configured as
outputs, these bits have no effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port B bit n.
1 Internal pull-up/pull-down device enabled for port B bit n.
6.5.2.4 Port B Slew Rate Enable Register (PTBSE)
R
W
Reset:
7
PTBSE7
0
6
PTBSE6
5
PTBSE5
4
PTBSE4
3
PTBSE3
2
PTBSE2
1
PTBSE1
0
0
0
0
0
0
Figure 6-14. Slew Rate Enable for Port B Register (PTBSE)
Table 6-12. PTBSE Register Field Descriptions
0
PTBSE0
0
Field
Description
7:0
PTBSE[7:0]
Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
88
Freescale Semiconductor