MC9S08EL32 Datasheet, PDF (83/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

6.5.1 Port A Registers
Port A is controlled by the registers listed below.
6.5.1.1 Port A Data Register (PTAD)
Chapter 6 Parallel Input/Output Control
R
W
Reset:
7
PTAD7
0
6
5
0
PTAD6
4
3
2
0
PTAD3
PTAD2
0
0
0
0
0
Figure 6-3. Port A Data Register (PTAD)
Table 6-1. PTAD Register Field Descriptions
1
PTAD1
0
0
PTAD0
0
Field
Description
7:6
PTAD[7:6]
3:0
PTAD[3:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
6.5.1.2 Port A Data Direction Register (PTADD)
R
W
Reset:
7
PTADD7
0
6
5
0
PTADD6
4
3
2
0
PTADD3
PTADD2
0
0
0
0
0
Figure 6-4. Port A Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
1
PTADD1
0
0
PTADD0
0
Field
Description
7:6
PTADD[7:6]
3:0
PTADD[3:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
83