MC9S08EL32 Datasheet, PDF (84/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output Control
6.5.1.3 Port A Pull Enable Register (PTAPE)
R
W
Reset:
7
PTAPE7
0
6
5
0
PTAPE6
4
3
2
1
0
PTAPE3
PTAPE2
PTAPE1
0
0
0
0
0
0
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
Table 6-3. PTAPE Register Field Descriptions
0
PTAPE0
0
Field
Description
7:0
PTAPE[7:6]
3:0
PTAPE[3:0]
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or internal
(pin interrupt only) pull-down device is enabled for the associated PTA pin. For port A pins that are configured as
outputs, these bits have no effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
6.5.1.4 Port A Slew Rate Enable Register (PTASE)
R
W
Reset:
7
PTASE7
0
6
5
0
PTASE6
4
3
2
1
0
PTASE3
PTASE2
PTASE1
0
0
0
0
0
0
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-4. PTASE Register Field Descriptions
0
PTASE0
0
Field
Description
7:6
PTASE[7:6]
3:0
PTASE[3:0]
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
84
Freescale Semiconductor