MC9S08EL32 Datasheet, PDF (192/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Field
6:4
RXFP
Table 12-2. SLCC2 Field Descriptions
Description
Receive Filter Prescaler — These bits configure the effective filter width for the digital receive filter circuit. The
RXFP bits control the maximum number of SLIC clock counts required for the filter to change state, which
determines the total maximum filter delay. Any pulse which is smaller than the maximum filter delay value will be
rejected by the filter and ignored as noise. For this reason, the user must choose the prescaler value
appropriately to ensure that all valid message traffic is able to pass the filter for the desired bit rate. For more
details about setting up the digital receive filter, please refer to Section 12.6.18, “Digital Receive Filter.”
The frequency of the SLIC clock must be between 2 MHz and 20 MHz, factoring in worst case possible numbers
due to untrimmed process variations, as well as temperature and voltage variations in oscillator frequency. This
will guarantee greater than 1.5% accuracy for all LIN messages from 1–20 kbps. The faster this input clock is,
the greater the resulting accuracy and the higher the possible bit rates at which the SLIC can send and receive.
In LIN systems, the bit rates will not exceed 20 kbps; however, the SLIC module is capable of much higher speeds
without any configuration changes, for cases such as high-speed downloads for reprogramming of FLASH
memory or diagnostics in a test environment where radiated emissions requirements are not as stringent. In
these situations, the user may choose to run faster than the 20 kbps limit which is imposed by the LIN
specification for EMC reasons. Details of how to calculate maximum bit rates and operate the SLIC above 20
kbps are detailed in .” Refer to Section 12.6.6, “SLIC Module Initialization Procedure,” for more information on
when to set up this register. See Table 12-3.
3
SLCWCM
SLIC Wait Clock Mode — This write-once bit can only be written once out of MCU reset state and should be
written before SLIC is first enabled.
0 SLIC clocks continue to run when the CPU is placed into wait mode so that the SLIC can receive messages
and wakeup the CPU.
1 SLIC clocks stop when the CPU is placed into wait mode
2
BTM¹
UART Byte Transfer Mode — Byte transmit mode bypasses the normal LIN message framing and checksum
monitoring and allows the user to send and receive single bytes in a method similar to a half-duplex UART. When
enabled, this mode reads the bit time register (SLCBT) value and assumes this is the value corresponding to the
number of SLIC clock counts for one bit time to establish the desired UART bit rate. The user software must
initialize this register prior to sending or receiving data, based on the input clock selection, prescaler stage
choice, and desired bit rate. If this bit is cleared during a byte transmission, that byte transmission is halted
immediately.
BTM treats any data length in SLCDLC as one byte (DLC = 0x00) and disables the checksum circuitry so that
CHKMOD has no effect. Refer to Section 12.6.16, “Byte Transfer Mode Operation,” for more detailed information
about how to use this mode. BTM sets up the SLIC module to send and receive one byte at a time, with 8-bit
data, no parity, and one stop bit (8-N-1). This is the most commonly used setup for UART communications and
should work for most applications. This is fixed in the SLIC and is not configurable.
0 UART byte transfer mode disabled
1 UART byte transfer mode enabled
0
SLCE
SLIC Module Enable — Controls the clock to the SLIC module
0 SLIC module disabled
1 SLIC module enabled
1 _{To guarantee timing, the user must ensure that the SLIC clock used allows the proper communications timing tolerances and}
therefore internal oscillator circuits might not be appropriate for use with BTM mode.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
194
Freescale Semiconductor