MC9S08EL32 Datasheet, PDF (191/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Table 12-1. SLCC1 Field Descriptions (continued)
Field
Description
2
TXABRT
1
IMSG
0
SLCIE
Transmit Abort Message
0 Normal operation
1 Transmitter aborts current transmission at next byte boundary; TXABRT resets to 0 after the transmission is
successfully aborted TXABRT also resets to 0 upon detection of a bit error.
SLIC Ignore Message Bit — IMSG cannot be cleared by a write of 0, but is cleared automatically by the SLIC
module after the next BREAK/SYNC symbol pair is validated. After it is set, IMSG will not keep data from being
written to the receive data buffer, which means that the buffers cannot be assumed to contain known valid
message data until the next receive buffer full interrupt. IMSG must not be used in BTM mode. The SLIC
automatically clears the IMSG bit when entering MCU STOP mode or MCU wait mode with SLCWCM bit set.
0 Normal operation1SLIC interrupts (except "No Bus Activity") are suppressed until the next message header
arrives
SLIC Interrupt Enable
0 SLIC interrupt sources are disabled
1 SLIC interrupt sources are enabled
12.3.2 SLIC Control Register 2 (SLCC2)
SLIC control register 2 (SLCC2) contains bits used to control various features of the SLIC module.
7
R
0
W
6
5
4
3
2
RXFP
SLCWCM
BTM
Reset
0
1
0
0
0
0
= Unimplemented or Reserved
Figure 12-5. SLIC Control Register 2 (SLCC2)
1
0
0
SLCE
0
0
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
193