MC9S08EL32 Datasheet, PDF (165/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 11
Inter-Integrated Circuit (S08IICV2)
11.1 Introduction
The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The
interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
NOTE
The SDA and SCL should not be driven above V_DD. These pins are
pseudo-open-drain containing a protection diode to V_DD.
11.1.1 Module Configuration
The IIC module pins, SDA and SCL, can be repositioned under software control using IICPS in SOPT1,
as as shown in Table 11-1. This bit selects which general-purpose I/O ports are associated with IIC
operation.
Table 11-1. IIC Position Options
SOPT1[IICPS]
Port Pin for SDA Port Pin for SCL
0 (default
1
PTA2
PTB6
PTA3
PTB7
Figure 11-1 shows the MC9S08EL32 Series and MC9S08SL16 Series block diagram with the IIC module
highlighted.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
165