MC9S08EL32 Datasheet, PDF (219/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

1 _{Bit rates over 120,000 bits per second are not recommended for LIN}
communications, as physical layer delay between the TX and RX pins can cause
the stop bit of a byte to be mis-sampled as the last data bit. This could result in a
byte framing error.
The above numbers assume a perfect input waveforms into the SLCRX pin, where 1 and 0 bits are of equal
length and are exactly the correct length for the appropriate speed. Factors such as physical layer wave
shaping and ground shift can affect the symmetry of these waveforms, causing bits to appear shortened or
lengthened as seen by the SLIC module. The user must take these factors into account and base the
maximum speed upon the shortest possible bit time that the SLIC module may observe, factoring in all
physical layer effects. On some LIN physical layer devices it is possible to turn off wave shaping circuitry
for high-speed operation, removing this portion of the physical layer error.
The digital receive filter can also affect high speed operation if it is set too low and begins to filter out valid
message traffic. Under ideal conditions, this will not happen, as the digital filter maximum speeds
allowable are higher than the speeds allowed for ±1.5% accuracy. If the digital receive filter prescaler is
set to divide-by-4; however, the filter delay is very close to the ±1.5% accuracy maximum bit time.
For example, with a SLIC clock of 4 MHz, the SLIC module is capable of maintaining ±1.5% accuracy up
to 60,000 bps. If the digital receive filter prescaler is set to divide-by-4, this means that the filter will only
pass message traffic which is 62,500 bps or slower under ideal circumstances. This is only a difference of
2,500 bps (4.17% of the nominal valid message traffic speed). In this case, the user must ensure that with
all errors accounted for, no bit will appear shorter than 16 μs
(1 bit at 62,500 bps) or the filter will block that bit. This is far too narrow a margin for safe design practices.
The better solution would be to reduce the filter prescaler, increasing the gap between the filter cut-off
point and the nominal speed of valid message traffic. Changing the prescaler to divide by 2 in this example
gives a filter cut-off of 125,000 bps, which is 60,000 bps faster than the nominal speed of the LIN bus and
much less likely to interfere with valid message traffic.
To ensure that all valid messages pass the filter stage in high-speed operation, it is best to ensure that the
filter cut-off point is at least 2 times the nominal speed of the fastest message traffic to appear on the bus.
Refer to Table 12-13 for a more complete list of the digital receive filter delays as they relate to the
maximum LIN bus frequency. Table 12-14 repeats much of the data found in Table 12-13; however, the
filter delay values (cutoff values) are shown in the frequency and time domains. Note that Table 12-14
shows the filter performance under ideal conditions.
When switching between a low-speed (< 4800 bps) to a high-speed (> 40000 bps) LIN message, the master
node must allow a minimum idle time of eight bit times (of the slowest bit rate) between the messages.
This prevents a valid message at another frequency from being detected as an invalid message.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
221