MC9S08EL32 Datasheet, PDF (221/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

SLIC
clock
(MHz)
2
Table 12-14. Digital Receive Filter Absolute Cutoff (Ideal Conditions)¹
Max Bit
Rate
(kbps)
Min Pulse
Width
Allowed
(μs)
RXFP = ÷8
15,625
64.00
Max Bit
Rate
(kbps)
Min Pulse
Width
Allowed
(μs)
RXFP = ÷7
17,857
56.00
Max Bit
Rate
(kbps)
Min Pulse
Width
Allowed
(μs)
RXFP = ÷6
20,833
48.00
Max Bit
Rate
(kbps)
Min Pulse
Width
Allowed
(μs)
RXFP = ÷5
25,000
40.00
RXFP = ÷4
RXFP = ÷3
RXFP = ÷2
RXFP = ÷1
20
312,500
3.20 416,667
2.40 625,000
1.60 1,250,000
0.80
18
281,250
3.56 375,000
2.67 562,500
1.78 1,125,000
0.89
16
250,000
4.00 333,333
3.00 500,000
2.00 1,000,000
1.00
14
218,750
4.57 291,667
3.43 437,500
2.29 875,000
1.14
12
187,500
5.33 250,000
4.00 375,000
2.67 750,000
1.33
10
156,250
6.40 208,333
4.80 312,500
3.20 625,000
1.60
8
125,000
8.00 166,667
6.00 250,000
4.00 500,000
2.00
6
93,750
10.67 125,000
8.00 187,500
5.33 375,000
2.67
4
62,500
16.00
83,333
12.00 125,000
8.00 250,000
4.00
2
31,250
32.00
41,667
24.00
62,500
16.00 125,000
8.00
1 _{Bit rates over 120,000 bits per second are not recommended for LIN communications, as physical layer delay between the}
TX and RX pins can cause the stop bit of a byte to be mis-sampled as the last data bit. This could result in a byte framing
error.
12.6.15 Bit Error Detection and Physical Layer Delay
The bit error detection circuitry of the SLIC module monitors the received bits to determine if they match
the state of the corresponding transmitted bits. The sampling of the receive line takes place near the end
of the bit being transmitted, so as long as the total physical layer delay does not exceed 75% of one bit
time, bit error detection will work properly. For normal LIN bus speeds (<= 20 kbps), the physical layer
delay in the system is typically significantly lower than 75% of a bit time and bit error detection should
remain enabled by the user.
If the physical layer delay begins to exceed 75% of one bit time, the received bits begin to significantly
lag behind the transmitted bits. In this case, it's possible for the bit error detection circuitry to falsely
sample the delayed 'previous' bit on the receive pin rather than the current bit. It is the responsibility of the
user to determine if the total physical layer delay is large enough to require disabling the bit error detection
circuitry. This should only be required at speeds higher than allowed in normal LIN operations.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
223