MC9S08EL32 Datasheet, PDF (33/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 3 Modes of Operation
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Table 3-1. Stop Mode Selection
STOPE ENBDM ¹ LVDE LVDSE PPDC
Stop Mode
0
x
1
1
x
x Stop modes disabled; illegal opcode reset if STOP instruction executed
x
x Stop3 with BDM enabled ²
1
0
Both bits must be 1 0 Stop3 with voltage regulator active
1
0
Either bit a 0
0 Stop3
1
0
Either bit a 0
1 Stop2
1 _{ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 17.4.1.1, “BDC Status and}
Control Register (BDCSCR)”.
2 _{When in Stop3 mode with BDM enabled, The SIDD will be near RIDD levels because internal clocks are enabled.}
3.6.1 Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Exit from stop3 is done by asserting RESET, or an asynchronous interrupt pin. The asynchronous interrupt
pins are PIA0-PIA3, PIB0 -PIB3, and PIC0-PIC7. Exit from stop3 can also be done by the low-voltage
detection (LVD) reset, the low-voltage warning (LVW) interrupt, the ADC conversion complete interrupt,
the analog comparator (ACMP) interrupt, the real-time counter (RTC) interrupt, the SLIC wake-up
interrupt, or the SCI receiver interrupt.
If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after
fetching the reset vector. Exit by means of an asynchronous interrupt, analog comparator interrupt, or the
real-time interrupt will result in the MCU fetching the appropriate interrupt vector.
3.6.1.1 LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate the LVD must be left enabled when entering stop3.
3.6.1.2 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in Chapter 17, “Development Support.” If ENBDM is set when the CPU executes a
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
33