MC9S08EL32 Datasheet, PDF (47/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 4 Memory
4.5 FLASH and EEPROM
The MC9S08EL32 Series and MC9S08SL16 Series includes FLASH and EEPROM memory intended
primarily for program and data storage. In-circuit programming allows the operating program and data to
be loaded into FLASH and EEPROM, respectively, after final assembly of the application product. It is
possible to program the arrays through the single-wire background debug interface. Because no special
voltages are needed for erase and programming operations, in-application programming is also possible
through other software-controlled communication paths. For a more detailed discussion of in-circuit and
in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale
Semiconductor document order number HCS08RMv1/D.
4.5.1 Features
Features of the FLASH and EEPROM memory include:
• Array size
— MC9S08EL32: 32,768 bytes of FLASH, 512 bytes of EEPROM
— MC9S08EL16: 16,384 bytes of FLASH, 512 bytes of EEPROM
— MC9S08SL16: 16,384 bytes of FLASH, 256 bytes of EEPROM
— MC9S08SL8: 8,192 bytes of FLASH, 256 bytes of EEPROM
• Sector size: 512 bytes for FLASH, 8 bytes for EEPROM
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection and vector redirection
• Security feature for FLASH, EEPROM, and RAM
4.5.2 Program and Erase Times
Before any program or erase command can be accepted, the FLASH and EEPROM clock divider register
(FCDIV) must be written to set the internal clock for the FLASH and EEPROM module to a frequency
(f_FCLK) between 150 kHz and 200 kHz (see Section 4.5.11.1, “FLASH and EEPROM Clock Divider
Register (FCDIV)”). This register can be written only once, so normally this write is performed during
reset initialization. FCDIV cannot be written if the access error flag, FACCERR in FSTAT, is set. The user
must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting
clock (1/f_FCLK) is used by the command processor to time program and erase pulses. An integer number
of these timing pulses is used by the command processor to complete a program or erase command.
Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (f_FCLK). The time for one cycle of FCLK is t_FCLK = 1/f_FCLK. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where t_FCLK = 5 μs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
47