MC9S08EL32 Datasheet, PDF (216/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

NOTE
Do not write the CHKMOD or data length values in SLCDLC more than
one time per message frame. The SLIC tracks the number of sent or received
bytes based on the value written to this register at the beginning of the data
field and rewriting this register will corrupt the checksum calculation and
cause unpredictable behavior in the SLIC module. The application software
must track the number of sent or received bytes to know what the current
byte count in the SLIC is. If programming in C, make sure to use the
STATIC modifier on this variable (or make it a global variable) to ensure
that it keeps its value between interrupts.
12.6.9.3 Transmit Abort
The transmit abort bit (TXABRT) in SLCC1 allows the user to cease transmission of data on the next byte
boundary. When this bit is set to 1, it will finish transmitting the byte currently being transmitted, then
cease transmission. After the transmission is successfully aborted, TXABRT will automatically be reset
by the SLIC to 0. If the SLIC is not in process of transmitting at the time TXABRT is written to 1, there is
no effect and TXABRT will read back as 0.
12.6.9.4 Possible Errors on Request Message Data
Possible errors on request message data are:
• Byte Framing Error
• Checksum-Error (LIN specified error)
• Bit-Error
12.6.10 Handling IMSG to Minimize Interrupts
The IMSG feature is designed to minimize the number of interrupts required to maintain LIN
communications. On a network with many slave nodes, it is very likely that a particular slave will observe
messages which are not intended for that node. When the SLIC module detects any message header, it
synchronizes to that message frame and bit rate, then interrupts the CPU after the identifier byte has been
successfully received and parity checked. At this time, if the software determines that the message may be
ignored, IMSG may be set to indicate to the module that the data field of the message frame is to be ignored
and no additional interrupts should be generated until the next valid message header is received. The bit is
automatically reset to 0 after the current message frame is complete and the LIN bus returns to idle state.
This reduces the load on the CPU and allows the application software to immediately begin performing
any operations which might otherwise not be allowed while receiving messaging.
NOTE
IMSG will prevent another interrupt from occurring for the current message
frame, however if data bytes are appearing on the bus they may be received
and copied into the message buffer. This will delete any previous data which
might have been present in the buffer, even though no interrupt is triggered
to indicate the arrival of this data.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
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Freescale Semiconductor