MC9S08EL32 Datasheet, PDF (225/356 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

UNFILTERED
RX DATA
FILTERED
RX DATA
(³1 PRESCALE)
FILTER CLOCK
(³1 PRESCALE)
16 FILTER CLOCKS
(³1 PRESCALE)
FILTER BEGINS
COUNTING DOWN
SLIC CLOCK
FILTER REACHES 0X0
AND TOGGLES FILTER OUTPUT
15 SLIC CLOCKS
(1/2 OF SLCBT VALUE)
16 FILTER CLOCKS
(³1 PRESCALE)
FILTER BEGINS
COUNTING UP
FILTER REACHES 0XF
AND TOGGLES FILTER OUTPUT
35 SLIC CLOCKS
(ACTUAL FILTERED BIT LENGTH)
IDEAL SLIC SAMPLE POINT (17 SLIC CLOCKS)
This example assumes a SLCBT value of 30 (0x1E).
Transmitted bits will be sent out as 30 SLIC clock cycles long.
SLIC SAMPLE POINT
(BASED ON SLCBT VALUE)
The proper closest SLCBT setting would be 34 (0x22),
which gives the ideal sample point of 17 SLIC clocks and
transmitted bits are 34 SLIC clocks long.
Figure 12-21. BTM Mode Receive Byte Sampling Example
The error also comes into effect with transmitted bit times. Using the previous example with a SLCBT
value of 34, transmitted bits will appear as 34 SLIC clock periods long. This is one SLIC clock short of
the proper length. Depending on the frequency of the SLIC clock, one period of the SLIC clock might be
a large or a small fraction of one ideal bit time. Raising the frequency of the SLIC clock will reduce this
error relative to the ideal bit time, improving the resolution of the SLIC clock relative to the bit rate of the
bus. In any case, the error is still one SLIC clock cycle. Raising the SLIC clock frequency, however,
requires programming a higher value for SLCBT to maintain the same target bit rate.
Smaller values of SLCBT combined with higher values of the SLIC clock frequency (smaller clock period)
will give faster bit rates, but the SLIC clock period becomes an increasingly significant portion of one bit
time.
Because BTM mode does not perform any synchronization and relies on the accuracy of the data provided
by the user software to set its sample point and generate transmitted bits, the constraint on maximum
speeds is only limited to the limits imposed by the digital filter delay and the SLIC input clock. Because
the digital filter delay cannot be less than 16 SLIC clock cycles, the fastest possible pulse which would
pass the filter is 16 clock periods at 8 MHz, or 500,000 bits/second. The values shown in Table 12-14 are
the same values shown in Table 12-15 and indicate the absolute fastest bit rates which could just pass the
minimum digital filter settings (prescaler = divide by 1) under perfect conditions.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
227