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MC9S12XD64MAA Datasheet, PDF (86/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.3.2.3 Reserved Register (CTFLG)
This register is reserved for factory testing of the CRG module and is not available in normal modes.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-6. Reserved Register (CTFLG)
Read: Always reads 0x_00 in normal modes
Write: Unimplemented in normal modes
NOTE
Writing to this register when in special mode can alter the CRG
fucntionality.
2.3.2.4 CRG Flags Register (CRGFLG)
This register provides CRG status bits and ï¬ags.
R
W
Reset
7
RTIF
0
6
PORF
1
5
LVRF
2
4
LOCKIF
0
3
LOCK
0
2
TRACK
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset.
= Unimplemented or Reserved
Figure 2-7. CRG Flags Register (CRGFLG)
Read: Anytime
Write: Refer to each bit for individual write conditions
Table 2-2. CRGFLG Field Descriptions
1
SCMIF
0
0
SCM
0
Field
7
RTIF
6
PORF
Description
Real Time Interrupt Flag â RTIF is set to 1 at the end of the RTI period. This ï¬ag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
Power on Reset Flag â PORF is set to 1 when a power on reset occurs. This ï¬ag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
MC9S12XDP512 Data Sheet, Rev. 2.21
86
Freescale Semiconductor
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