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MC9S12XD64MAA Datasheet, PDF (175/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.7 ATD Status Register 0 (ATDSTAT0)
This read-only register contains the sequence complete ï¬ag, overrun ï¬ags for external trigger and FIFO
mode, and the conversion counter.
7
R
SCF
W
6
5
4
3
0
0
ETORF
FIFOR
Reset
0
0
0
0
0
= Unimplemented or Reserved
2
CC2
0
1
CC1
0
0
CC0
0
Figure 5-9. ATD Status Register 0 (ATDSTAT0)
Read: Anytime
Write: Anytime (No effect on (CC2, CC1, CC0))
Table 5-17. ATDSTAT0 Field Descriptions
Field
7
SCF
5
ETORF
4
FIFOR
2â0
CC[2:0]
Description
Sequence Complete Flag â This ï¬ag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN = 1), the ï¬ag is set after each one is completed. This ï¬ag is
cleared when one of the following occurs:
A) Write â1â to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and read of a result register
0 Conversion sequence not completed
1 Conversion sequence has completed
External Trigger Overrun Flag â While in edge trigger mode (ETRIGLE = 0), if additional active edges are
detected while a conversion sequence is in process the overrun ï¬ag is set. This ï¬ag is cleared when one of the
following occurs:
A) Write â1â to ETORF
B) Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No External trigger over run error has occurred
1 External trigger over run error has occurred
FIFO Over Run Flag â This bit indicates that a result register has been written to before its associated
conversion complete ï¬ag (CCF) has been cleared. This ï¬ag is most useful when using the FIFO mode because
the ï¬ag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been over written before it has been read
(i.e., the old data has been lost). This ï¬ag is cleared when one of the following occurs:
A) Write â1â to FIFOR
B) Start a new conversion sequence (write to ATDCTL5 or external trigger)
0 No over run has occurred
1 An over run condition exists
Conversion Counter â These 3 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. E.g. CC2 = 1, CC1 = 1,
CC0 = 0 indicates that the result of the current conversion will be in ATD result register 6. If in non-FIFO mode
(FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in
FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its
maximum value is reached.
Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the
conversion counter even if FIFO=1.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
175
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