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MC9S12XD64MAA Datasheet, PDF (228/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 6 XGATE (S12XGATEV2)
BFFO
Bit Field Find First One
BFFO
Operation
FirstOne (RS) â RD;
Searches the ï¬rst â1â in register RS (from MSB to LSB) and writes the bit position into the destination
register RD. The upper bits of RD are cleared. In case the content of RS is equal to $0000, RD will be
cleared and the carry ï¬ag will be set. This is used to distinguish a â1â in position 0 versus no â1â in the
whole RS register at all.
CCR Effects
NZVC
0â0â
N: 0; cleared.
Z: Set if the result is $0000; cleared otherwise.
V: 0; cleared.
C: Set if RS = $00001; cleared otherwise.
1 Before executing the instruction
Code and CPU Cycles
Source Form
BFFO RD, RS
Address
Mode
DYA
00001
Machine Code
RD
RS
Cycles
10000
P
MC9S12XDP512 Data Sheet, Rev. 2.21
228
Freescale Semiconductor
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