MC9S12XD64MAA Datasheet, PDF (753/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0

Chapter 20 S12X Debug (S12XDBGV3) Module
20.3.2.4 Debug Control Register2 (DBGC2)
Address: 0x0023
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
CDCM
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-6. Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Table 20-13. DBGC2 Field Descriptions
1
0
ABCM
0
0
Field
Description
3–2
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
CDCM[1:0] described in Table 20-14.
1–0
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
ABCM[1:0] described in Table 20-15.
CDCM
00
01
10
11
ABCM
00
01
10
11
Table 20-14. CDCM Encoding
Description
Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
Match2 mapped to comparator C/D inside range....... Match3 disabled.
Match2 mapped to comparator C/D outside range....... Match3 disabled.
Reserved
Table 20-15. ABCM Encoding
Description
Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
Match 0 mapped to comparator A/B inside range....... Match1 disabled.
Match 0 mapped to comparator A/B outside range....... Match1 disabled.
Reserved
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
755