MC9S12XD64MAA Datasheet, PDF (318/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Register
Name
Bit 7
6
5
4
3
2
1
TC1H (High) R TC15
TC14
TC13
TC12
TC11
TC10
TC9
W
TC1H (Low) R TC7
TC6
TC5
TC4
TC3
TC2
TC1
W
TC2H (High) R TC15
TC14
TC13
TC12
TC11
TC10
TC9
W
TC2H (Low) R TC7
TC6
TC5
TC4
TC3
TC2
TC1
W
TC3H (High) R TC15
TC14
TC13
TC12
TC11
TC10
TC9
W
TC3H (Low) R TC7
TC6
TC5
TC4
TC3
TC2
TC1
W
= Unimplemented or Reserved
Figure 7-2. ECT Register Summary (Sheet 5 of 5)
7.3.2.1 Timer Input Capture/Output Compare Select Register (TIOS)
R
W
Reset
7
IOS7
0
6
IOS6
5
IOS5
4
IOS4
3
IOS3
2
IOS2
1
IOS1
0
0
0
0
0
0
Figure 7-3. Timer Input Capture/Output Compare Register (TIOS)
Read or write: Anytime
All bits reset to zero.
Table 7-2. TIOS Field Descriptions
Field
7:0
IOS[7:0]
Description
Input Capture or Output Compare Channel Configuration
0 The corresponding channel acts as an input capture.
1 The corresponding channel acts as an output compare.
Bit 0
TC8
TC0
TC8
TC0
TC8
TC0
0
IOS0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
318
Freescale Semiconductor