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MC9S12XD64MAA Datasheet, PDF (443/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Field
7:0
AC[7:0]
Table 10-21. CANIDAR4âCANIDAR7 Register Field Descriptions
Description
Acceptance Code Bits â AC[7:0] comprise a user-deï¬ned sequence of bits with which the corresponding bits
of the related identiï¬er register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identiï¬er mask register.
10.3.2.18 MSCAN Identiï¬er Mask Registers (CANIDMR0âCANIDMR7)
The identiï¬er mask register speciï¬es which of the corresponding bits in the identiï¬er acceptance register
are relevant for acceptance ï¬ltering. To receive standard identiï¬ers in 32 bit ï¬lter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to âdonât care.â
To receive standard identiï¬ers in 16 bit ï¬lter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to âdonât care.â
Module Base + 0x0014 (CANIDMR0)
0x0015 (CANIDMR1)
0x0016 (CANIDMR2)
0x0017 (CANIDMR3)
R
W
Reset
7
AM7
0
6
AM6
0
R
W
Reset
7
AM7
0
6
AM6
0
R
W
Reset
7
AM7
0
6
AM6
0
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
5
AM5
0
5
AM5
0
5
AM5
0
4
AM4
0
4
AM4
0
4
AM4
0
4
AM4
0
3
AM3
0
3
AM3
0
3
AM3
0
3
AM3
0
2
AM2
0
2
AM2
0
2
AM2
0
2
AM2
0
1
AM1
0
1
AM1
0
1
AM1
0
1
AM1
0
0
AM0
0
0
AM0
0
0
AM0
0
0
AM0
0
Figure 10-22. MSCAN Identiï¬er Mask Registers (First Bank) â CANIDMR0âCANIDMR3
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
443
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