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MC9S12XD64MAA Datasheet, PDF (450/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Read: For transmit buffers, anytime when TXEx ï¬ag is set (see Section 10.3.2.7, âMSCAN Transmitter
Flag Register (CANTFLG)â) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 10.3.2.11, âMSCAN Transmit Buffer Selection Register (CANTBSEL)â). For receive buffers,
only when RXF ï¬ag is set (see Section 10.3.2.5, âMSCAN Receiver Flag Register (CANRFLG)â).
Write: For transmit buffers, anytime when TXEx ï¬ag is set (see Section 10.3.2.7, âMSCAN Transmitter
Flag Register (CANTFLG)â) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 10.3.2.11, âMSCAN Transmit Buffer Selection Register (CANTBSEL)â). Unimplemented for
receive buffers.
Reset: Undeï¬ned (0x00XX) because of RAM-based implementation
Figure 10-25. Receive/Transmit Message Buffer â Standard Identiï¬er Mapping
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
IDR0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
W
R
IDR1
ID2
ID1
ID0
RTR
IDE (=0)
W
R
IDR2
W
R
IDR3
W
= Unused, always read âxâ
10.3.3.1 Identiï¬er Registers (IDR0âIDR3)
The identiï¬er registers for an extended format identiï¬er consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identiï¬er registers for a standard format identiï¬er consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
10.3.3.1.1 IDR0âIDR3 for Extended Identiï¬er Mapping
R
W
Reset:
7
ID28
6
ID27
5
ID26
4
ID25
3
ID24
2
ID23
1
ID22
x
x
x
x
x
x
x
Figure 10-26. Identiï¬er Register 0 (IDR0) â Extended Identiï¬er Mapping
0
ID21
x
MC9S12XDP512 Data Sheet, Rev. 2.21
450
Freescale Semiconductor
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