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MC9S12XD64MAA Datasheet, PDF (346/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.28 Pulse Accumulator B Flag Register (PBFLG)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
PBOVF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-50. Pulse Accumulator B Flag Register (PBFLG)
Read: Anytime
Write used in the ï¬ag clearing mechanism. Writing a one to the ï¬ag clears the ï¬ag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the ï¬ag cannot be cleared via the normal ï¬ag clearing
mechanism (writing a one to the ï¬ag). Reference Section 7.3.2.6, âTimer
System Control Register 1 (TSCR1)â.
All bits reset to zero.
PBFLG indicates when interrupt conditions have occurred. The ï¬ag can be cleared via the normal ï¬ag
clearing mechanism (writing a one to the ï¬ag) or via the fast ï¬ag clearing mechanism (Reference TFFCA
bit in Section 7.3.2.6, âTimer System Control Register 1 (TSCR1)â).
Table 7-36. PBFLG Field Descriptions
Field
1
PBOVF
Description
Pulse Accumulator B Overï¬ow Flag â This bit is set when the 16-bit pulse accumulator B overï¬ows from
0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overï¬ows from 0x00FF to 0x0000.
When PACMX = 1, PBOVF bit can also be set if 8-bit pulse accumulator 1 (PAC1) reaches 0x00FF and an active
edge follows on PT1.
MC9S12XDP512 Data Sheet, Rev. 2.21
346
Freescale Semiconductor
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