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MC9S12XD64MAA Datasheet, PDF (107/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 2 Clocks and Reset Generator (S12CRGV6)
CME
0
1
1
1
SCME
X
0
1
1
Table 2-12. Outcome of Clock Loss in Wait Mode
SCMIE
CRG Actions
X
Clock failure -->
No action, clock loss not detected.
X
Clock failure -->
CRG performs Clock Monitor Reset immediately
Clock failure -->
Scenario 1: OSCCLK recovers prior to exiting wait mode.
â MCU remains in wait mode,
â VREG enabled,
â PLL enabled,
â SCM activated,
â Start clock quality check,
â Set SCMIF interrupt ï¬ag.
Some time later OSCCLK recovers.
â CM no longer indicates a failure,
â 4096 OSCCLK cycles later clock quality check indicates clock o.k.,
â SCM deactivated,
â PLL disabled depending on PLLWAI,
â VREG remains enabled (never gets disabled in wait mode).
â MCU remains in wait mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
â Exit wait mode using OSCCLK as system clock (SYSCLK),
0
â Continue normal operation.
or an External Reset is applied.
â Exit wait mode using OSCCLK as system clock,
â Start reset sequence.
Scenario 2: OSCCLK does not recover prior to exiting wait mode.
â MCU remains in wait mode,
â VREG enabled,
â PLL enabled,
â SCM activated,
â Start clock quality check,
â Set SCMIF interrupt ï¬ag,
â Keep performing clock quality checks (could continue inï¬nitely) while in wait mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
â Exit wait mode in SCM using PLL clock (fSCM) as system clock,
â Continue to perform additional clock quality checks until OSCCLK is o.k. again.
or an External RESET is applied.
â Exit wait mode in SCM using PLL clock (fSCM) as system clock,
â Start reset sequence,
â Continue to perform additional clock quality checks until OSCCLKis o.k.again.
Clock failure -->
â VREG enabled,
â PLL enabled,
â SCM activated,
1
â Start clock quality check,
â SCMIF set.
SCMIF generates self clock mode wakeup interrupt.
â Exit wait mode in SCM using PLL clock (fSCM) as system clock,
â Continue to perform a additional clock quality checks until OSCCLK is o.k. again.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
107
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