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MC9S12XD64MAA Datasheet, PDF (424/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Register
Name
0x0014â0x0017 R
CANIDMRx
W
Bit 7
AM7
6
AM6
5
AM5
4
AM4
3
AM3
2
AM2
1
AM1
0x0018â0x001B R
CANIDAR4â7 W AC7
AC6
AC5
AC4
AC3
AC2
AC1
0x001Câ0x001F R
CANIDMR4â7 W
AM7
AM6
AM5
AM4
AM3
AM2
AM1
0x0020â0x002F R
CANRXFG
W
See Section 10.3.3, âProgrammerâs Model of Message Storageâ
0x0030â0x003F R
CANTXFG
W
See Section 10.3.3, âProgrammerâs Model of Message Storageâ
= Unimplemented or Reserved
u = Unaffected
Figure 10-3. MSCAN Register Summary (continued)
Bit 0
AM0
AC0
AM0
10.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated ï¬gure number. Details of register bit and ï¬eld
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
10.3.2.1 MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
7
R
RXFRM
W
6
RXACT
5
CSWAI
4
SYNCH
3
TIME
2
WUPE
1
SLPRQ
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 10-4. MSCAN Control Register 0 (CANCTL0)
NOTE
The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the
reset state when the initialization mode is active (INITRQ = 1 and
INITAK = 1). This register is writable again as soon as the initialization
mode is exited (INITRQ = 0 and INITAK = 0).
Read: Anytime
0
INITRQ
1
MC9S12XDP512 Data Sheet, Rev. 2.21
424
Freescale Semiconductor
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